Advantech MMP3-21 Manual do Utilizador Página 59
- Página / 112
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
Advantech SOM-Express Design Guide
Chapter 5 Carrier Board Design Guidelines 59
5.5 LVDS
5.5.1 Signal Description
Table 5-15 shows SOM-Express LVDS signals, including pin number, signals, I/0 and
descriptions.
Table 5-15 LVDS signals description
Pin Signal I/O Description
A71,73,75,78
A72,74,76,79
LVDS_A[0:3]+
LVDS_A[0:3]-
O LVDS Channel A differential pairs
A81
A82
LVDS_A_CK+
LVDS_A_CK-
O LVDS Channel A differential clock
B71,73,75,77
B72,74,76,78
LVDS_B[0:3]+
LVDS_B[0:3]-
O LVDS Channel B differential pairs
B81
B82
LVDS_B_CK+
LVDS_B_CK-
O LVDS Channel B differential clock
A77 LVDS_VDD_EN O LVDS panel power enable
B79 LVDS_BKLT_EN O LVDS panel backlight enable
B83 LVDS_BKLT_CTRL O LVDS panel backlight brightness control
A83 LVDS_I2C_CK O I2C clock output for LVDS display use
A84 LVDS_I2C_DAT O I2C data line for LVDS display use
5.5.2 Design Guideline
Figure 5-22 shows LVDS LCD connections.
Figure 5-22 LVDS LCD Connections
5.5.2.1 Package Length Constraints
Skew minimization requires chipset die-pad to LVDS connector trace length matching
of the LVDS signal pairs that belong to the same group including the clock strobe
signals of that group. The reason for this is to compensate for the package length
variation across each signal group in order to minimize timing variance. The chipset
does not equalize package lengths internally, SOM-Express compensates for the
mismatch length. Please be sure to be trace length matched on the carrier board.
Table LV-2 shows the LVDS Signals Trace Length Mismatch Mapping.
Each LVDS signal should be trace length matched to its associated clock strobe
within ±10 mils. The Channel A clock strobe pair must also be trace length matched
to the Channel B clock strobe pair within ±10 mils.
- Advantech 1
- Notices 2
- Revision History 2
- Table of Contents 3
- 4 Table of Contents 4
- Table of Contents 5 5
- 6 Table of Contents 6
- Table of Contents 7 7
- 8 Table of Contents 8
- Chapter 1 Introduction 9
- 1.2 Referenced Documents 10
- 2.1 Overview 11
- 2.2 Specifications 13
- 2.2.1 SOM-5780 14
- 2.2.2 SOM-5782 16
- 2.2.3 SOM-DB5700 18
- 2.3 System Resources 19
- 2.3.1 SOM-5780 Resources 19
- 2.3.2 SOM-5782 Resources 22
- 2.4 PCI Routing 25
- 2.5 DC Specifications 25
- 2.5.1 Interface I/O Voltage 25
- 2.5.1.3 Audio 27
- 2.5.1.4 VGA 27
- 2.5.1.5 LCD 28
- 2.5.1.6 IDE 28
- 2.5.1.7 Ethernet 28
- 2.5.1.8 TV-Out Bus 28
- 2.5.1.9 IrDA 28
- 2.6 AC Specification 29
- 2.6.1 PCI-Bus AC Spec 29
- 2.6.3 Audio AC Spec 29
- 2.6.4 VGA AC Spec 29
- 2.6.5 IDE AC Spec 30
- 2.6.6 I2C AC Spec 30
- 2.6.7 SMBus AC Spec 30
- Chapter 3 Pin Assignments 31
- 3.1 Row A 32
- 3.2 Row B 33
- 3.3 Row C 34
- 3.4 Row D 35
- 4.1 Nominal Board Stack-Up 36
- Thickness 37
- 4.3 Alternate Stack Ups 39
- 5.1 PCI-Bus 40
- 5.1.1 Signal Description 40
- 5.1.2 Design Guidelines 41
- Vtest 0.4 Vcc 1.5 V 42
- Tskew 2 (max) 2 (max) ns 42
- 5.1.3 Layout Guidelines 44
- Carrier 45
- 5.1.4 Application Notes 46
- 5.2.1 Signal Description 47
- 5.2.2 Design Guidelines 47
- 5.2.3 Layout Guideline 48
- SOM-Express 49
- USB Connector 49
- 5.2.3.4 Stubs 50
- 5.3.1 Signal Description 51
- 5.3.2 Design Guidelines 51
- 5.3.2.3 Azalia: 52
- Analog Ground 53
- 5.3.3 Layout Guidelines 54
- ± 15% 54
- 5.4 VGA 56
- 5.4.1 Signal Description 56
- 5.4.2 Design Guidelines 57
- 5.4.3 Layout Guideline 57
- VGA Connector 58
- 5.5 LVDS 59
- 5.5.1 Signal Description 59
- 5.5.2 Design Guideline 59
- 5.5.3 Layout Requirements 60
- 5.6 Primary IDE0 61
- 5.6.1 Signal Description 61
- 5.6.2 Design Guidelines 61
- IDE bus IDE cable 62
- Total Max 62
- Length 13 inches 62
- Carrier Board 62
- 5.6.3 Layout Guidelines 63
- 5.7 Ethernet 64
- 5.7.1 Signal Descriptions 64
- 5.7.2 Design Guidelines 64
- LAN Connector 65
- 5.7.3 Layout Guidelines 66
- 5.7.3.2 Transformer 67
- 5.7.3.3 Critical Dimensions 68
- 5.8 TV-Out 70
- 5.8.1 Signal Descriptions 70
- 5.8.2 Design Guidelines 70
- TV DAC Filter 71
- 5.9 Miscellaneous 72
- Carrier board 74
- 5.10 PCI Express Bus 77
- 5.10.1 Signal Description 77
- Pin Signal I/O Description 77
- 5.10.3.1 Differential pairs 81
- Guidelines 82
- L1 L2 L3 Capacitor Value 83
- L1 L2 Capacitor Value 83
- 5.11 Serial ATA 84
- 5.11.1 Signal Description 84
- 5.11.2 Design Guidelines 84
- 5.11.3 Layout Guidelines 85
- 5.12 LPC 87
- 5.12.1 Signal Description 87
- 5.12.2 Design Guidelines 87
- 5.12.3 Layout Guidelines 87
- 5.12.4 Application Notes 88
- 5.12.4.3 LPT/Floppy 89
- 5.12.4.4 EMI Considerations 89
- Parallel Port 90
- 6.2 Design Guidelines 95
- 8.1 Material of Heatsink 101
- 8.4 Grounding Issues 102
- 8.8.1 Vendor List 106
- 8.8.2 Heat-Spreader 106
- 8.8.3 Heat-Sink 107
- 8.8.4 Thermal Pad 108
- M2.5*6 5 109
- M2.5*16 5 109
- Quantity 109
- 8.8.6 Fan 110
Manuais e produtos relacionados com Barebones PC/estação de trabalho Advantech MMP3-21
(30 páginas)© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.049 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais