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Advantech SOM-Express Design Guide
Chapter 5 Carrier Board Design Guidelines 79
in scenarios #1 and #3. The specification does not include any provisions to address
scenario #2
! Polarity Inversion
The PCI Express spec requires polarity inversion to be supported independently by
all receivers across the link, i.e. the positive signal from the transmitter (TX+) can
connect to the negative signal of the receiver (RX-) in the same lane. Of course that
means the negative signal from the transmitter (TX-) must now also connect to the
positive signal of the receiver (RX+) in such a scenario. Figure 5-44 shows an
example. But be careful, it is important that polarity inversion does not direction
inversion, i.e. the TX differential pair from one device must still connect to the RX
differential pair on the receiver device.
Figure 5-44 Polarity Inversion on a TX to RX Interconnect
! Lane Reversal
Lane reversal allows the lane number to be switched from high to low and low to high.
For example the lane 15 from the SOM-Express would connect to lane 0 of the
device, and lane 0 from the SOM-Express would connect to lane 15 of the device.
Lane reversal need only be supported by one of the devices in the link to allow its
implementation. It is important to note that similar to polarity inversion, Lane Reversal
does not imply direction reversal, i.e. the TX differential pair from an upstream device
must still connect to the RX differential pair on the downstream device. Figure 5-45
shows an example.
Figure 5-45 Lane Reversal and Polarity Inversion - TX to RX Interconnect
Note: Lane Reversal is not supported for multiplexed SDVO signals on the external
graphics using the PCI Express architecture interface.
RX
+
RX -
TX +
TX -
TX
+
TX -
RX -
RX +
RX+
RX -
TX+
TX -
RX+
RX -
TX+
TX -
Correct Wrong
TX [0]+
TX [0] -
TX [1]+
TX [1] -
RX [0]+
RX [0] -
RX [1]+
RX [1] -
RX [1]+
RX [1] -
RX [0]+
RX [0] -
TX [1] -
TX [1] +
TX [0] -
TX [0] +
TX [0]+
TX [0] -
TX [1]+
TX [1] -
RX [0]+
RX [0] -
RX [1]+
RX [1] -
RX [1]+
RX [1] -
RX [0]+
RX [0] -
TX [1]+
TX [1] -
TX [0]+
TX [0] -
TX [0]+
TX [0] -
TX [1]+
TX [1] -
RX [0]+
RX [0] -
RX [1]+
RX [1] -
RX [1]+
RX [1] -
RX [0]+
RX [0] -
TX [1]+
TX [1] -
TX [0]+
TX [0] -
Device 1 Device 2
Pin 1
Device 1 Device 2
Pin 1
Device 1 Device 2
Pin 1
(TX [0]+)
(TX [0] -)
(TX [1]+)
(TX [1] -)
(RX [0]+)
(RX [0] -)
(RX [1]+)
(RX [1] -)
(RX [1]+)
(RX [1] -)
(RX [0]+)
(RX [0] -)
(RX [1] -)
(RX [1]+)
(RX [0] -)
(RX [0]+)
Lane
Reversal
Polarity
Inversion
- Advantech 1
- Notices 2
- Revision History 2
- Table of Contents 3
- 4 Table of Contents 4
- Table of Contents 5 5
- 6 Table of Contents 6
- Table of Contents 7 7
- 8 Table of Contents 8
- Chapter 1 Introduction 9
- 1.2 Referenced Documents 10
- 2.1 Overview 11
- 2.2 Specifications 13
- 2.2.1 SOM-5780 14
- 2.2.2 SOM-5782 16
- 2.2.3 SOM-DB5700 18
- 2.3 System Resources 19
- 2.3.1 SOM-5780 Resources 19
- 2.3.2 SOM-5782 Resources 22
- 2.4 PCI Routing 25
- 2.5 DC Specifications 25
- 2.5.1 Interface I/O Voltage 25
- 2.5.1.3 Audio 27
- 2.5.1.4 VGA 27
- 2.5.1.5 LCD 28
- 2.5.1.6 IDE 28
- 2.5.1.7 Ethernet 28
- 2.5.1.8 TV-Out Bus 28
- 2.5.1.9 IrDA 28
- 2.6 AC Specification 29
- 2.6.1 PCI-Bus AC Spec 29
- 2.6.3 Audio AC Spec 29
- 2.6.4 VGA AC Spec 29
- 2.6.5 IDE AC Spec 30
- 2.6.6 I2C AC Spec 30
- 2.6.7 SMBus AC Spec 30
- Chapter 3 Pin Assignments 31
- 3.1 Row A 32
- 3.2 Row B 33
- 3.3 Row C 34
- 3.4 Row D 35
- 4.1 Nominal Board Stack-Up 36
- Thickness 37
- 4.3 Alternate Stack Ups 39
- 5.1 PCI-Bus 40
- 5.1.1 Signal Description 40
- 5.1.2 Design Guidelines 41
- Vtest 0.4 Vcc 1.5 V 42
- Tskew 2 (max) 2 (max) ns 42
- 5.1.3 Layout Guidelines 44
- Carrier 45
- 5.1.4 Application Notes 46
- 5.2.1 Signal Description 47
- 5.2.2 Design Guidelines 47
- 5.2.3 Layout Guideline 48
- SOM-Express 49
- USB Connector 49
- 5.2.3.4 Stubs 50
- 5.3.1 Signal Description 51
- 5.3.2 Design Guidelines 51
- 5.3.2.3 Azalia: 52
- Analog Ground 53
- 5.3.3 Layout Guidelines 54
- ± 15% 54
- 5.4 VGA 56
- 5.4.1 Signal Description 56
- 5.4.2 Design Guidelines 57
- 5.4.3 Layout Guideline 57
- VGA Connector 58
- 5.5 LVDS 59
- 5.5.1 Signal Description 59
- 5.5.2 Design Guideline 59
- 5.5.3 Layout Requirements 60
- 5.6 Primary IDE0 61
- 5.6.1 Signal Description 61
- 5.6.2 Design Guidelines 61
- IDE bus IDE cable 62
- Total Max 62
- Length 13 inches 62
- Carrier Board 62
- 5.6.3 Layout Guidelines 63
- 5.7 Ethernet 64
- 5.7.1 Signal Descriptions 64
- 5.7.2 Design Guidelines 64
- LAN Connector 65
- 5.7.3 Layout Guidelines 66
- 5.7.3.2 Transformer 67
- 5.7.3.3 Critical Dimensions 68
- 5.8 TV-Out 70
- 5.8.1 Signal Descriptions 70
- 5.8.2 Design Guidelines 70
- TV DAC Filter 71
- 5.9 Miscellaneous 72
- Carrier board 74
- 5.10 PCI Express Bus 77
- 5.10.1 Signal Description 77
- Pin Signal I/O Description 77
- 5.10.3.1 Differential pairs 81
- Guidelines 82
- L1 L2 L3 Capacitor Value 83
- L1 L2 Capacitor Value 83
- 5.11 Serial ATA 84
- 5.11.1 Signal Description 84
- 5.11.2 Design Guidelines 84
- 5.11.3 Layout Guidelines 85
- 5.12 LPC 87
- 5.12.1 Signal Description 87
- 5.12.2 Design Guidelines 87
- 5.12.3 Layout Guidelines 87
- 5.12.4 Application Notes 88
- 5.12.4.3 LPT/Floppy 89
- 5.12.4.4 EMI Considerations 89
- Parallel Port 90
- 6.2 Design Guidelines 95
- 8.1 Material of Heatsink 101
- 8.4 Grounding Issues 102
- 8.8.1 Vendor List 106
- 8.8.2 Heat-Spreader 106
- 8.8.3 Heat-Sink 107
- 8.8.4 Thermal Pad 108
- M2.5*6 5 109
- M2.5*16 5 109
- Quantity 109
- 8.8.6 Fan 110
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