Advantech MMP3-21 Manual do Utilizador Página 77
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Advantech SOM-Express Design Guide
Chapter 5 Carrier Board Design Guidelines 77
5.10 PCI Express Bus
SOM-Express provides a PCI Express Bus interface that is compliant with the PCI
Express
*
Base Specification, Revision 1.0a. It supports several general purpose PCI
Express port (x1) and external graphics using PCI Express architecture (x16). For
more information on the PCI Express Bus interface, refer to the PCI Express
*
Base
Specification, Revision 1.0a.
5.10.1 Signal Description
Table 5-23 shows SOM-Express PCI Express bus signals for general purpose, Table
5-24 shows PCI Express bus signal for external graphics. Table 5-25 shows
ExpressCard Support signals. Each table includes pin number, signals, I/0, and
descriptions.
Table 5-23 PCIE Signal Description(General purpose)
Pin Signal I/O Description
A68,64,61,58,55,52
A69,65,62,59,56,53
PCIE_TX[0:5]+
PCIE_TX[0:5]-
O PCI Express Differential Transmit Pairs 0 through 5
B68,64,61,58,55,52
B69,65,62,59,56,53
PCIE_RX[0:5]+
PCIE_RX[0:5]-
I PCI Express Differential Receive Pairs 0 through 5
-
PCIE_TX[16:31]+
PCIE_TX[16:31]-
O
PCI Express Differential Transmit Pairs 16 through 31
These are same line as PEG_TX[0:15]+ and -
-
PCIE_RX[16:31]+
PCIE_RX[16:31]-
I
PCI Express Differential Receive Pairs 16 through 31
These are same line as PEG_TX[0:15]+ and -
A88
A89
PCIE_CLK_REF+
PCIE_CLK_REF-
O Reference clock output for all PCI Express Graphics lanes.
B66 WAKE0# I PCI Express wakeup signal.
Table 5-24 PEG Signal Description(x16 Graphics)
Pin Signal I/O Description
-
PEG_TX[0:15]+
PEG_TX[0:15]-
O
PCI Express Graphics Transmit Differential Pairs 0 through 15
Some of these are multiplexed with SDVO lines.
-
PEG_RX[0:15]+
PEG_RX[0:15]-
I
PCI Express Graphics Receive Differential Pairs 0 through 15
Some of these are multiplexed with SDVO lines.
D54 PEG_LANE_RV# I
PCI Express Graphics lane reversal input strap. Pull low on the
carrier board to reverse lane order. Be aware that the SDVO lines
that share this interface do not necessarily reverse order if this s
strap is low.
D97 PEG_ENABLE#- I
Strap to enable PCI Express x16 external graphics interface. Pull low
to disable internal graphics and enable the x16 interface.
Table 5-25 Express Card Support
Pin Signal I/O Description
A49,B48 EXCD[0:1]_CPPE# I
PCI ExpressCard: PCI Express capable card request, active low,
one per card
A48,B47 EXCD[0:1]_RST# O PCI ExpressCard: reset, active low, one per card
- Advantech 1
- Notices 2
- Revision History 2
- Table of Contents 3
- 4 Table of Contents 4
- Table of Contents 5 5
- 6 Table of Contents 6
- Table of Contents 7 7
- 8 Table of Contents 8
- Chapter 1 Introduction 9
- 1.2 Referenced Documents 10
- 2.1 Overview 11
- 2.2 Specifications 13
- 2.2.1 SOM-5780 14
- 2.2.2 SOM-5782 16
- 2.2.3 SOM-DB5700 18
- 2.3 System Resources 19
- 2.3.1 SOM-5780 Resources 19
- 2.3.2 SOM-5782 Resources 22
- 2.4 PCI Routing 25
- 2.5 DC Specifications 25
- 2.5.1 Interface I/O Voltage 25
- 2.5.1.3 Audio 27
- 2.5.1.4 VGA 27
- 2.5.1.5 LCD 28
- 2.5.1.6 IDE 28
- 2.5.1.7 Ethernet 28
- 2.5.1.8 TV-Out Bus 28
- 2.5.1.9 IrDA 28
- 2.6 AC Specification 29
- 2.6.1 PCI-Bus AC Spec 29
- 2.6.3 Audio AC Spec 29
- 2.6.4 VGA AC Spec 29
- 2.6.5 IDE AC Spec 30
- 2.6.6 I2C AC Spec 30
- 2.6.7 SMBus AC Spec 30
- Chapter 3 Pin Assignments 31
- 3.1 Row A 32
- 3.2 Row B 33
- 3.3 Row C 34
- 3.4 Row D 35
- 4.1 Nominal Board Stack-Up 36
- Thickness 37
- 4.3 Alternate Stack Ups 39
- 5.1 PCI-Bus 40
- 5.1.1 Signal Description 40
- 5.1.2 Design Guidelines 41
- Vtest 0.4 Vcc 1.5 V 42
- Tskew 2 (max) 2 (max) ns 42
- 5.1.3 Layout Guidelines 44
- Carrier 45
- 5.1.4 Application Notes 46
- 5.2.1 Signal Description 47
- 5.2.2 Design Guidelines 47
- 5.2.3 Layout Guideline 48
- SOM-Express 49
- USB Connector 49
- 5.2.3.4 Stubs 50
- 5.3.1 Signal Description 51
- 5.3.2 Design Guidelines 51
- 5.3.2.3 Azalia: 52
- Analog Ground 53
- 5.3.3 Layout Guidelines 54
- ± 15% 54
- 5.4 VGA 56
- 5.4.1 Signal Description 56
- 5.4.2 Design Guidelines 57
- 5.4.3 Layout Guideline 57
- VGA Connector 58
- 5.5 LVDS 59
- 5.5.1 Signal Description 59
- 5.5.2 Design Guideline 59
- 5.5.3 Layout Requirements 60
- 5.6 Primary IDE0 61
- 5.6.1 Signal Description 61
- 5.6.2 Design Guidelines 61
- IDE bus IDE cable 62
- Total Max 62
- Length 13 inches 62
- Carrier Board 62
- 5.6.3 Layout Guidelines 63
- 5.7 Ethernet 64
- 5.7.1 Signal Descriptions 64
- 5.7.2 Design Guidelines 64
- LAN Connector 65
- 5.7.3 Layout Guidelines 66
- 5.7.3.2 Transformer 67
- 5.7.3.3 Critical Dimensions 68
- 5.8 TV-Out 70
- 5.8.1 Signal Descriptions 70
- 5.8.2 Design Guidelines 70
- TV DAC Filter 71
- 5.9 Miscellaneous 72
- Carrier board 74
- 5.10 PCI Express Bus 77
- 5.10.1 Signal Description 77
- Pin Signal I/O Description 77
- 5.10.3.1 Differential pairs 81
- Guidelines 82
- L1 L2 L3 Capacitor Value 83
- L1 L2 Capacitor Value 83
- 5.11 Serial ATA 84
- 5.11.1 Signal Description 84
- 5.11.2 Design Guidelines 84
- 5.11.3 Layout Guidelines 85
- 5.12 LPC 87
- 5.12.1 Signal Description 87
- 5.12.2 Design Guidelines 87
- 5.12.3 Layout Guidelines 87
- 5.12.4 Application Notes 88
- 5.12.4.3 LPT/Floppy 89
- 5.12.4.4 EMI Considerations 89
- Parallel Port 90
- 6.2 Design Guidelines 95
- 8.1 Material of Heatsink 101
- 8.4 Grounding Issues 102
- 8.8.1 Vendor List 106
- 8.8.2 Heat-Spreader 106
- 8.8.3 Heat-Sink 107
- 8.8.4 Thermal Pad 108
- M2.5*6 5 109
- M2.5*16 5 109
- Quantity 109
- 8.8.6 Fan 110
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