Advantech MMP3-21 Manual do Utilizador Página 61
- Página / 112
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
Advantech SOM-Express Design Guide
Chapter 5 Carrier Board Design Guidelines 61
5.6 Primary IDE0
SOM-Express provides one IDE interface.
5.6.1 Signal Description
Table 5-17 shows SOM-Express IDE signals, including pin number, signals, I/0 and
descriptions.
Table 5-17 IDE signals description
Pin Signal I/O Description
- IDE_D[0..15] I/O Bidirectional data to/from IDE device
D13,14,15 IDE_A[0..2] O Address lines to IDE device
D16 IDE_CS1# O IDE Device Chip Select for 1F0h to 1FF0h range
D17 IDE_CS3# O IDE Device Chip Select for 3F0h to 3FF0h range
D8 IDE_REQ I
IDE DMA Request for IDE Master. This is the input pin from
the IDE DMA request to do the IDE Master Transfer. It will
active high in DMA or Ultra-33 mode and always be inactive
low in PIO mode.
D10 IDE_ACK# O IDE device DMA Acknowledge
C13 IDE_IORDY I
IDE device I/O ready input
Pull low by the IDE device, active low
C14 IDE_IOR# O I/O ready line to IDE device
D9 IDE_IOW# O
I/O write line to IDE device
Data latched on trailing (rising) edge
D12 IDE_IRQ I Interrupt request from IDE device
D18 IDE_RESET# O Low active hardware reset (RSTISA inverted).
D77 IDE_CBLID# O
Input from off-module hardware indicating the type of IDE
cable being used. High indicates a 40-pin cable used for
legacy IDE modes. Low indicates that an 80 pin cable with
interleaved grounds is used. Such a cable is required for
Ultra-DMA 66, 100 and 133 modes.
5.6.2 Design Guidelines
5.6.2.1 Design Considerations
The IDE port can support two hard drives or other ATAPI devices. The two devices
on the port are wired in parallel, which is accomplished by plugging both drives into a
single flat ribbon cable equipped with two socket connectors. A jumper is typically
manually set on each device to set it for master or slave operation. If two devices are
used in the master/slave mode on the same IDE port, the IDE_CBLID# pins of both
devices must be connected together. These pairs of pins negotiate between the
master and slave devices. The devices may not function correctly unless these pins
are interconnected. If two devices are plugged into a single IDE cable, the cable will
interconnect the pins properly. If the two devices on one port are integrated on the
carrier board or plugged into separate connectors, care should be taken to tie the
corresponding pins together.
- Advantech 1
- Notices 2
- Revision History 2
- Table of Contents 3
- 4 Table of Contents 4
- Table of Contents 5 5
- 6 Table of Contents 6
- Table of Contents 7 7
- 8 Table of Contents 8
- Chapter 1 Introduction 9
- 1.2 Referenced Documents 10
- 2.1 Overview 11
- 2.2 Specifications 13
- 2.2.1 SOM-5780 14
- 2.2.2 SOM-5782 16
- 2.2.3 SOM-DB5700 18
- 2.3 System Resources 19
- 2.3.1 SOM-5780 Resources 19
- 2.3.2 SOM-5782 Resources 22
- 2.4 PCI Routing 25
- 2.5 DC Specifications 25
- 2.5.1 Interface I/O Voltage 25
- 2.5.1.3 Audio 27
- 2.5.1.4 VGA 27
- 2.5.1.5 LCD 28
- 2.5.1.6 IDE 28
- 2.5.1.7 Ethernet 28
- 2.5.1.8 TV-Out Bus 28
- 2.5.1.9 IrDA 28
- 2.6 AC Specification 29
- 2.6.1 PCI-Bus AC Spec 29
- 2.6.3 Audio AC Spec 29
- 2.6.4 VGA AC Spec 29
- 2.6.5 IDE AC Spec 30
- 2.6.6 I2C AC Spec 30
- 2.6.7 SMBus AC Spec 30
- Chapter 3 Pin Assignments 31
- 3.1 Row A 32
- 3.2 Row B 33
- 3.3 Row C 34
- 3.4 Row D 35
- 4.1 Nominal Board Stack-Up 36
- Thickness 37
- 4.3 Alternate Stack Ups 39
- 5.1 PCI-Bus 40
- 5.1.1 Signal Description 40
- 5.1.2 Design Guidelines 41
- Vtest 0.4 Vcc 1.5 V 42
- Tskew 2 (max) 2 (max) ns 42
- 5.1.3 Layout Guidelines 44
- Carrier 45
- 5.1.4 Application Notes 46
- 5.2.1 Signal Description 47
- 5.2.2 Design Guidelines 47
- 5.2.3 Layout Guideline 48
- SOM-Express 49
- USB Connector 49
- 5.2.3.4 Stubs 50
- 5.3.1 Signal Description 51
- 5.3.2 Design Guidelines 51
- 5.3.2.3 Azalia: 52
- Analog Ground 53
- 5.3.3 Layout Guidelines 54
- ± 15% 54
- 5.4 VGA 56
- 5.4.1 Signal Description 56
- 5.4.2 Design Guidelines 57
- 5.4.3 Layout Guideline 57
- VGA Connector 58
- 5.5 LVDS 59
- 5.5.1 Signal Description 59
- 5.5.2 Design Guideline 59
- 5.5.3 Layout Requirements 60
- 5.6 Primary IDE0 61
- 5.6.1 Signal Description 61
- 5.6.2 Design Guidelines 61
- IDE bus IDE cable 62
- Total Max 62
- Length 13 inches 62
- Carrier Board 62
- 5.6.3 Layout Guidelines 63
- 5.7 Ethernet 64
- 5.7.1 Signal Descriptions 64
- 5.7.2 Design Guidelines 64
- LAN Connector 65
- 5.7.3 Layout Guidelines 66
- 5.7.3.2 Transformer 67
- 5.7.3.3 Critical Dimensions 68
- 5.8 TV-Out 70
- 5.8.1 Signal Descriptions 70
- 5.8.2 Design Guidelines 70
- TV DAC Filter 71
- 5.9 Miscellaneous 72
- Carrier board 74
- 5.10 PCI Express Bus 77
- 5.10.1 Signal Description 77
- Pin Signal I/O Description 77
- 5.10.3.1 Differential pairs 81
- Guidelines 82
- L1 L2 L3 Capacitor Value 83
- L1 L2 Capacitor Value 83
- 5.11 Serial ATA 84
- 5.11.1 Signal Description 84
- 5.11.2 Design Guidelines 84
- 5.11.3 Layout Guidelines 85
- 5.12 LPC 87
- 5.12.1 Signal Description 87
- 5.12.2 Design Guidelines 87
- 5.12.3 Layout Guidelines 87
- 5.12.4 Application Notes 88
- 5.12.4.3 LPT/Floppy 89
- 5.12.4.4 EMI Considerations 89
- Parallel Port 90
- 6.2 Design Guidelines 95
- 8.1 Material of Heatsink 101
- 8.4 Grounding Issues 102
- 8.8.1 Vendor List 106
- 8.8.2 Heat-Spreader 106
- 8.8.3 Heat-Sink 107
- 8.8.4 Thermal Pad 108
- M2.5*6 5 109
- M2.5*16 5 109
- Quantity 109
- 8.8.6 Fan 110
Manuais e produtos relacionados com Barebones PC/estação de trabalho Advantech MMP3-21
(30 páginas)© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.067 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais